Computer Architecture and Lab A - EModule Computer Architecture
Academic Year 2024/2025 - Teacher: EMILIANO ALESSIO TRAMONTANAExpected Learning Outcomes
Knowledge and understanding: To acquire knowledge and understanding of fundamental concepts of computer systems architecture and of methodological principles that drive its development, in the historical perspective of their evolution.
Applying knowledge and understanding: To acquire problem solving capabilities in computer system design, by trying to solve on-purpose proposed problems, and abilities to make use of, to design and to implement software tools, such as simulators and interpreters, for abstract machines at the lowest levels of computer system organization.
Making judgements: To be able to compare and evaluate the quality of solutions to design problems for computer systems.
Communication skills: To acquire communication skills and proper language to communicate, even with nonexpert people, about problems relating to functioning, design, implementation, and evaluation of computer systems.
Learning skills: To develop the ability to adapt one's own knowledge to the rapid evolution of the discipline and to keep up-to-date through specialized sources in the field.
Course Structure
Classroom lectures and lab tutorials with exercises.
Slides used for the lessons are given in the web page of the teacher on the website of the Laurea degree (www.dmi.unict.it/tramonta/)
Should teaching be carried out in mixed mode or remotely, it may be necessary to introduce changes with respect to previous statements, in line with the programme planned and outlined in the syllabus.
Students having some disabilities should communicate, sufficiently before the exam date, the teacher, the CInAP responsible in the DMI and CInAP that they want to have some assistance during the exam, the type of such assistance will be described by CInAP.
Required Prerequisites
Attendance of Lessons
Detailed Course Content
Introduction to computers using categories, and the main functional components. Representation of numbers and characters using the binary system. Methods for hardware parallelization. Brief history of computers, and generations of computers.
RISC and CISC architectures, addressing modes. Types and formats of RISC instructions, examples of Assembly language programs in RISC. Stack management and subroutines. Logical instructions, shifting, rotation. CISC instruction set.
Input/output operations, access to I/O devices, receiving and serving interrupts.
Support software, assembly languages and C, operating system.
Base structure of the processor, hardware components for RISC architectures: register bank, ALU, data path, instruction fetching section. Execution steps, jumps, memory waiting. Wired control and control signals. CISC processors, bus architecture, microprogrammed control.
Pipeline organization, pipeline problems, data dependency, memory delays, jump delays, resource limitations. Pipeline performance evaluation. Superscalar processors.
Input/output system, bus structure, synchronous, asynchronous buses, bus arbitration.
Memory system, static, dynamic memories, memory cells, chip memory organization. Memory hierarchy, address schemes and replacement for cache memory.
Efficient circuits for binary arithmetic.
Textbook Information
C. Hamacher, Z. Vranesic, S. Zaky & N. Manjikian : Introduzione all'architettura dei calcolatori. Third italian edition, McGraw-Hill Education (Italy), 2013
Course Planning
| Subjects | Text References | |
|---|---|---|
| 1 | Introduction to the course, computer categories, functional components | C. 1 |
| 2 | Instructions, execution, performance, technological generations | C. 1 |
| 3 | Memory, addressing, operations, instructions, RTN notation, additions, addressing modes, assembling | C. 2 |
| 4 | Stack, subroutines, parameter passing by registers and stack, activation areas | C. 2 |
| 5 | Arithmetic and logic operations, CISC instructions, flags, instructions codification | C. 2 |
| 6 | I/O operations, interrupts, interrupt service routine, multiple interrupts, interrupt handler | C. 3 |
| 7 | Tools for assembly languages, brief introduction to operating systems | C. 4 |
| 8 | Hardware components, stages, register files, data path, address generator, execution steps, jumps | C. 5 |
| 9 | Control signals, wired control, generation of control signals, CISC architecture, microprogrammed control | C. 5 |
| 10 | Pipeline, data dependence, delays for memory and for jumps | C. 6 |
| 11 | Jum predictions, automata, jump buffer, performance, superscalar architecture and its problems | C. 6 |
| 12 | Bus: synchronous, multi cycle, asynchronous, arbitration | C. 7 |
| 13 | Memory devices, memory hierarchy, static and dynamic memory | C. 8 |
| 14 | Memory modules and their organization, locality principles, cache hit and cache miss | C. 8 |
| 15 | Direct, associative, and group addressing, stale data, substitution algorithms, performance | C. 8 |
| 16 | Circuits for binary operations | C. 9 |
Learning Assessment
Learning Assessment Procedures
The exam consists of a written test and oral interview. The written test takes place at 9:00 AM on the day of the exam, unless otherwise communicated. The written test lasts one hour and consists of various multiple-choice questions and two open-ended questions that require code implementation and the drawing of diagrams. Passing the written test allows you to proceed to the oral part of the exam, which will be scheduled on days following the written test and communicated in advance.
An excellent evaluation of the written test will be given when the number of correct answers to multiple-choice questions is close to the total number of questions, and when the answers to the open-ended questions are correct and precise.
The exam will be evaluated excellently if you demonstrate a deep understanding of the course concepts and precision in their presentation. An intermediate grade will be given in cases where the exam shows a partial understanding of the topics. A barely passing grade will be awarded when, despite partial knowledge of the topics, they are presented superficially.
Students need to book their exam using the website SmartEdu.
The completion and presentation of a project are optional.
The assessment of learning may also be conducted remotely if conditions require it.
Examples of frequently asked questions and / or exercises
Convert from binary to decimal and vice versa
Logic gates and their truth tables
Instructions in Assembly and Assembly programs
Data path for program execution
Execution in pipeline